@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
@N: FX493 |Applying initial value "00000000" on instance cap1298_i2c_u3.keys_status[7:0] 
@N: FX493 |Applying initial value "00" on instance cap1298_i2c_u3.state_back[1:0] 
@N: FX493 |Applying initial value "00000000" on instance cap1298_i2c_u3.keys_status[7:0] 
@N: FX493 |Applying initial value "00" on instance cap1298_i2c_u3.state_back[1:0] 
@N: FX493 |Applying initial value "00000000" on instance cap1298_i2c_u3.keys_status[7:0] 
@N: FX493 |Applying initial value "00" on instance cap1298_i2c_u3.state_back[1:0] 
@N: FX493 |Applying initial value "00000000000" on instance num_status[10:0] 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: MT611 :|Automatically generated clock cap1298_i2c_0|clk_200khz_derived_clock is not used and is being removed
@N: MT611 :|Automatically generated clock cap1298_i2c_1|clk_200khz_derived_clock is not used and is being removed
@N: MT611 :|Automatically generated clock cap1298_i2c_2|clk_200khz_derived_clock is not used and is being removed
@N: FX1056 |Writing EDF file: C:\Users\TEST\Desktop\calculator_fpga\calculator_cap1298\impl1\cap1298_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
